Title :
ESD phenomena in graded junction devices
Author :
Duvvury, Charvaka ; Rountree, R.N. ; Stiegler, H.J. ; Polgreen, T. ; Corum, D.
Author_Institution :
Texas Instrum. Inc., Houston, TX, USA
Abstract :
The current very large-scale integration (VLSI) chips for sub-2-μm processes use some form of graded junction devices for process reliability. Electrostatic discharge (ESD) performance for these graded junction processes is examined by studying the process variations. The results show that the ESD protection level can be optimized without significantly compromising the hot carrier reliability or the circuit drive current. The unique failure modes in these devices are also discussed. The results are supported by transient thermal analysis simulations
Keywords :
MOS integrated circuits; electrostatic discharge; failure analysis; integrated circuit testing; thermal analysis; ESD protection level; NMOS devices; VLSI chips; circuit drive current; failure modes; graded junction devices; hot carrier reliability; process reliability; transient thermal analysis simulations; Analytical models; Electrostatic discharge; Failure analysis; Hot carriers; Instruments; MOS devices; MOSFET circuits; Protection; Silicides; Transient analysis;
Conference_Titel :
Reliability Physics Symposium, 1989. 27th Annual Proceedings., International
Conference_Location :
Phoenix, AZ
DOI :
10.1109/RELPHY.1989.36320
