Title :
Systolic architecture for integer point matrix multiplication using FPGA
Author :
Sonawane, D.N. ; Sutaone, M.S. ; Malek, Inayat
Author_Institution :
Dept. of Instrum. & Control Coll. of Eng., Pune M.S., Pune
Abstract :
The paper presents a systolic architecture for integer point matrix multiplication algorithm using FPGA. Approach uses four processing elements that minimizes resources, reduces the routing complexity and improves Area/Speed metric.
Keywords :
field programmable gate arrays; matrix multiplication; parallel algorithms; systolic arrays; FPGA; integer point matrix multiplication; integer point matrix multiplication algorithm; routing complexity; systolic architecture; Clocks; Computer architecture; Digital signal processing; Educational institutions; Field programmable gate arrays; Frequency; Instruments; Logic; Signal processing algorithms; Telecommunication control; FPGA; Systolic architecture; matrix multiplication; processing element (PE);
Conference_Titel :
Industrial Electronics and Applications, 2009. ICIEA 2009. 4th IEEE Conference on
Conference_Location :
Xi´an
Print_ISBN :
978-1-4244-2799-4
Electronic_ISBN :
978-1-4244-2800-7
DOI :
10.1109/ICIEA.2009.5138921
