A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os

Author

Ng, Hiok-Tiaq ; Lee, M. J Edward ; Farjad-Rad, Ramin ; Senthinathan, Ramesh ; Dally, William J. ; Nguyen, Anhtuyet ; Rathi, Rohit ; Greer, Trey ; Poulton, John ; Edmondson, John ; Tran, James

Author_Institution

Velio Commun. Inc., Milpitas, CA, USA

fYear

2003

fDate

21-24 Sept. 2003

Firstpage

77

Lastpage

80

Abstract

A 0.622-8 Gb/s CDR circuit using injection locking for jitter suppression and phase interpolation in high bandwidth SOC solutions is described. A slave injection locked oscillator (SILO) is locked to a tracking aperture-multiplying DLL (TA-MDLL) via a coarse phase selection MUX. For the fine timing vernier, an interpolator DAC controls the injection strength of the MUX output into the SILO. This 1.2 V 0.13 μm CMOS CDR consumes 33 mW at 8 Gb/s. Die area, including voltage regulator, is 0.08 mm². Recovered clock jitter is 6.9 ps rms/49.3 ps peak-to-peak at a 200 ppm bitrate offset.

Keywords

CMOS integrated circuits; clocks; delay lock loops; digital-analogue conversion; injection locked oscillators; jitter; multiplying circuits; synchronisation; voltage regulators; 0.13 micron; 1.2 V; 33 mW; 8 Gbit/s; CMOS CDR; CMOS clock multiplier; SILO; clock/data recovery circuits; coarse phase selection MUX; fine timing vernier; high bandwidth SOC; highly integrated I/O; injection locking; interpolator DAC; jitter suppression; phase interpolation; recovered clock jitter; slave injection locked oscillator; tracking aperture-multiplying DLL; voltage regulator; Bandwidth; Bit rate; Circuits; Clocks; Injection-locked oscillators; Interpolation; Jitter; Regulators; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003

Print_ISBN

0-7803-7842-3

Type

conf

DOI

10.1109/CICC.2003.1249363

Filename

1249363