Fast implementation of Wyner-Ziv Video codec using GPGPU

Author

Oh, Ryanggeun ; Park, Jongbin ; Jeon, Byeungwoo

Author_Institution

Dept. of Mobile Syst. Eng., Sungkyunkwan Univ., Suwon, South Korea

fYear

2010

fDate

24-26 March 2010

Firstpage

1

Lastpage

5

Abstract

In this paper, we report a fast implementation of Wyner-Ziv video decoder using general-purpose computing on graphics processing units (GPGPU). Despite of its many advantages, Wyner-Ziv video coding has a problem of huge decoding complexity. Since Slepian-Wolf decoding with rate adaptive LDPC accumulate code takes up more than 90% of entire Wyner-Ziv video decoding complexity, in this paper, we focus on fast implementation of the Slepian-Wolf decoder using the CUDA (Compute Unified Device Architecture) which is a GPGPU architecture developed by NVIDIA. Our implementation is shown to be 4~5 times (QCIF size) or 15~20 times (CIF size) faster compared to conventional Slepian-Wolf decoding.

Keywords

adaptive codes; computer graphic equipment; decoding; microprocessor chips; parallel architectures; parity check codes; video codecs; video coding; GPGPU architecture; Slepian-Wolf decoding; Wyner-Ziv video codec; Wyner-Ziv video coding; Wyner-Ziv video decoder; compute unified device architecture; decoding complexity; general-purpose computing on graphics processing units; rate adaptive LDPC accumulate code; Computer architecture; Decoding; Discrete cosine transforms; Mobile communication; Mobile computing; Parity check codes; Systems engineering and theory; Transform coding; Video codecs; Video coding; CUDA; GPGPU; Rate adaptive low density parity check code (LDPCA); Wyner-Ziv video coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Broadband Multimedia Systems and Broadcasting (BMSB), 2010 IEEE International Symposium on

Conference_Location

Shanghai

Print_ISBN

978-1-4244-4461-8

Electronic_ISBN

978-1-4244-4462-5

Type

conf

DOI

10.1109/ISBMSB.2010.5463150

Filename

5463150