A sub-mW MPEG-4 motion estimation processor core for mobile video application

Author

Miyakoshi, J. ; Kuroda, Y. ; Miyama, M. ; Imamura, K. ; Hashimoto, H. ; Yoshimoto, M.

Author_Institution

Fac. of Eng., Kanazawa Univ., Japan

fYear

2003

fDate

21-24 Sept. 2003

Firstpage

181

Lastpage

184

Abstract

This paper describes a sub-mW motion estimation processor core for MPEG-4 video encoding. It features a gradient descent search algorithm combined with a sub block search method that reduces required computation power to 8 MOPS, maintaining high picture quality as equivalent as a full search method, and an optimized SIMD datapath architecture to decrease the clock frequency and operating voltage. It has been designed with CMOS 5-metal 0.18 μm rules. The estimated power consumption to process a QCIF 15 fps video is less than 1 mW at 1.70 MHz at 1.0 V.

Keywords

CMOS digital integrated circuits; gradient methods; integrated circuit design; logic design; motion estimation; parallel processing; video coding; 0.18 micron; 1 mW; 1.0 V; 1.70 MHz; CMOS; MPEG-4 motion estimation processor core; QCIF video; full search method; gradient descent search algorithm; mobile video applications; optimized SIMD datapath architecture; picture quality; sub block search method; video encoding; Clocks; Computer architecture; Encoding; Energy consumption; Frequency; MPEG 4 Standard; Motion estimation; Optimization methods; Search methods; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003

Print_ISBN

0-7803-7842-3

Type

conf

DOI

10.1109/CICC.2003.1249386

Filename

1249386