DocumentCode
2345485
Title
A unified model for partial-depletion and full-depletion SOI circuit designs: using BSIMPD as a foundation
Author
Su, Pin ; Fung, Samuel K H ; Wyatt, Peter W. ; Wan, Hui ; Chan, Mansun ; Niknejad, Ali M. ; Hu, Chenming
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear
2003
fDate
21-24 Sept. 2003
Firstpage
241
Lastpage
244
Abstract
We present our approach to developing a unified SOI MOSFET model for circuit designs using state-of-the-art SOI technologies. Using BSIMPD as a foundation, we unify the PD and FD models by the concept of body-source built-in potential lowering. This unification is crucial due to the coexistence of PD/FD devices in a single chip as well as the coexistence of PD/FD behavior in a single device. The unified BSIMSOI model has been implemented in Berkeley SPICE3f4 and many commercial circuit simulators.
Keywords
MOSFET; circuit simulation; semiconductor device models; silicon-on-insulator; BSIMPD; SOI circuit design; SPICE; Si-SiO2; body-source built-in potential lowering; circuit simulators; full-depletion models; partial-depletion models; unified SOI MOSFET model; Capacitance; Circuit simulation; Circuit synthesis; Circuit testing; Councils; Diodes; Laboratories; MOSFET circuits; Vehicles; Virtual manufacturing;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003
Print_ISBN
0-7803-7842-3
Type
conf
DOI
10.1109/CICC.2003.1249395
Filename
1249395
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