Title :
False path analysis based on a hierarchical control representation
Author :
Kountouris, Apostolos A. ; Wolinski, Christophe
Author_Institution :
IRISA, Rennes, France
Abstract :
False path analysis is an activity with applications in a variety of computer science and engineering domains like for instance high-level synthesis, worst case execution time estimation, software testing etc. In this paper a method to automate false path analysis, based on a control flow graph connected to a hierarchical BDD based control representation, is described. By its ability to reason on predicate expressions involving arithmetic inequalities, this method overcomes certain limitations of previous approaches. Preliminary experimental results confirm its effectiveness
Keywords :
binary decision diagrams; data flow analysis; control flow graph; false path analysis; hierarchical BDD; high-level synthesis; worst case execution time; Application software; Arithmetic; Automatic control; Binary decision diagrams; Clocks; Computer science; Flow graphs; High level synthesis; Processor scheduling; Software testing;
Conference_Titel :
System Synthesis, 1998. Proceedings. 11th International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
0-8186-8623-5
DOI :
10.1109/ISSS.1998.730597
