A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics

Author

Su, Ke-Wei ; Sheu, Yi-Ming ; Lin, Chung-Kai ; Yang, Sheng-Jier ; Liang, Wen-Jya ; Xi, Xuemei ; Chiang, Chung-Shi ; Her, Jaw-Kang ; Chia, Yu-Tai ; Diaz, Carlos H. ; Hu, Chenming

Author_Institution

Taiwan Semicond. Manuf. Co., Hsin-Chu, Taiwan

fYear

2003

fDate

21-24 Sept. 2003

Firstpage

245

Lastpage

248

Abstract

This paper demonstrates a new compact and scaleable model of mechanical stress effects on MOS electrical performance, induced by shallow trench isolation (STI). This model has included the influence of STI stress not only on the mobility and saturation velocity, but also on the threshold voltage and other important second-order effects. Thus it could simulate the layout dependence of MOS performance with good accuracy and efficiency. We have verified this model with various device dimensions and layout styles of our advanced MOS technologies. And it shows the importance of this new model for circuit design in advanced CMOS generations.

Keywords

MIS devices; isolation technology; semiconductor device models; stress analysis; CMOS circuit design; MOS electrical characteristics layout dependence; STI mechanical stress effects; mobility; saturation velocity; shallow trench isolation; threshold voltage; Analytical models; CMOS technology; Circuit simulation; Circuit synthesis; Electric variables; MOS devices; Semiconductor device modeling; Semiconductor process modeling; Stress; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003

Print_ISBN

0-7803-7842-3

Type

conf

DOI

10.1109/CICC.2003.1249396

Filename

1249396