DocumentCode :
2345525
Title :
A defect-tolerant WSI file memory system using address permutation scheme for spare allocation
Author :
Fujiwara, Eiji ; Tanaka, Masaharu
Author_Institution :
Dept. of Comput. Sci., Tokyo Inst. of Technol., Japan
fYear :
1993
fDate :
27-29 Oct 1993
Firstpage :
183
Lastpage :
190
Abstract :
The authors propose a large capacity high-speed file memory system implemented with wafer scale RAM which adopts novel defect-tolerant technique. The defective memory blocks in the wafer are repaired by switching with the spare ones based on set-associative mapping. In order to repair the clustered defective blocks, these are permuted logically with other blocks by adding some constant value to the input block address. The defective blocks remained even after applying the above two methods are repaired by using error correcting codes which also correct soft errors induced by alpha particles in an on-line operation. With using the proposed technique, the authors demonstrate a large capacity high-speed WSI file memory system implemented with high fabrication yield and low redundancy rate
Keywords :
wafer-scale integration; address permutation; alpha particles; clustered defective blocks; defect-tolerant WSI file memory; error correcting codes; high fabrication yield; high-speed file memory; low redundancy rate; on-line operation; repair; set-associative mapping; soft errors; spare allocation; switching; Alpha particles; Computer science; DRAM chips; Disk drives; Error correction codes; Fabrication; Random access memory; Read-write memory; Redundancy; Wafer scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1993., The IEEE International Workshop on
Conference_Location :
Venice
ISSN :
1550-5774
Print_ISBN :
0-8186-3502-9
Type :
conf
DOI :
10.1109/DFTVS.1993.595772
Filename :
595772
Link To Document :
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