Title :
Concurrent error detection at architectural level
Author :
Bolchini, C. ; Fornaciari, W. ; Salice, F. ; Sciuto, D.
Author_Institution :
Dipt. di Elettronica e Inf., Politecnico di Milano, Italy
Abstract :
A methodology for designing systems with concurrent error detection capability is introduced. The proposed approach consists of a functional architecture and a checking architecture to verify data computed by the functional one. The methodology reduces both redundancy and latency through hardware resources and data sharing, respectively
Keywords :
error detection; high level synthesis; checking architecture; concurrent error detection; data sharing; functional architecture; hardware resources; latency; redundancy; Circuit synthesis; Computer architecture; Delay; Design methodology; Electronic equipment testing; Embedded system; Encoding; High level synthesis; Multiplexing; Proposals;
Conference_Titel :
System Synthesis, 1998. Proceedings. 11th International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
0-8186-8623-5
DOI :
10.1109/ISSS.1998.730600
