• DocumentCode
    2345720
  • Title

    A -107dBe, 10kHz carrier offset 2-GHz DLL-based frequency synthesizer

  • Author

    Zhuang, Jingcheng ; Du, Qingjin ; Kwasniewski, Tad

  • Author_Institution
    Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
  • fYear
    2003
  • fDate
    21-24 Sept. 2003
  • Firstpage
    301
  • Lastpage
    304
  • Abstract
    A low phase noise, low spur, DLL-based frequency synthesizer, utilizing a novel charge pump phase comparator and edge combining circuit to reduce the jitter and spur is reported. To prove its feasibility, a 9-time multiplication frequency synthesizer is designed and fabricated in 0.18 μm CMOS technology with an active area of 0.05 mm2. The output exhibits a spur power of -46.17dB below carrier and a phase noise of -107.17 dBc/Hz at 10 kHz offset with a reference frequency of 173 MHz from an RF generator.
  • Keywords
    CMOS integrated circuits; delay lock loops; frequency synthesizers; jitter; phase comparators; phase noise; 0.18 micron; 173 MHz; 2 GHz; CMOS; DLL-based frequency synthesizer; charge pump phase comparator; edge combining circuit; jitter reduction; low spur synthesizer; phase noise; spur power; synthesizer carrier offset; CMOS technology; Charge pumps; Circuits; Delay effects; Filters; Frequency synthesizers; Jitter; Phase noise; Pulse generation; Radio frequency;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003
  • Print_ISBN
    0-7803-7842-3
  • Type

    conf

  • DOI
    10.1109/CICC.2003.1249408
  • Filename
    1249408
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2345720