DocumentCode :
234580
Title :
Different configurations for dynamic latched comparators used in ultra low power Analog to Digital converters
Author :
Abozeid, Karim M. ; Aboudina, Mohamed M. ; Khalil, A.H.
Author_Institution :
Fac. of Eng., British Univ. in Egypt, Cairo, Egypt
fYear :
2014
fDate :
19-20 April 2014
Firstpage :
1
Lastpage :
6
Abstract :
This paper presents a comparison in the consumed power between different configurations of dynamic latched comparator used in low power Analog to Digital (A/D) converters especially the successive approximation register (SAR) which is used in many Electrical, Radio-frequency identification (RFID) and biomedical applications. This comparison is in architecture, consumed power and propagation time delay. The comparison is done under constant input referred offset.
Keywords :
analogue-digital conversion; comparators (circuits); flip-flops; A/D converter; RFID application; SAR; biomedical application; constant input referred offset; dynamic latched comparator; electrical application; power consumption; radiofrequency identification application; successive approximation register; time delay propagation; ultralow power analog to digital converter; Clocks; Equations; Mathematical model; Signal resolution; Analog to Digital converter (ADC); Least significant bit (LSB); Radio-frequency identification (RFID); Successive approximation register (SAR); Track and Latch (T/L);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Engineering and Technology (ICET), 2014 International Conference on
Conference_Location :
Cairo
Type :
conf
DOI :
10.1109/ICEngTechnol.2014.7016771
Filename :
7016771
Link To Document :
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