Optimization of phase-locked loop circuits via geometric programming

Author

Colleran, David M. ; Portmann, Clemenz ; Hassibi, Arash ; Crusius, César ; Mohan, Sunderarajan S. ; Boyd, Stephen ; Lee, Thomas H. ; Hershenson, Maria Del Mar

Author_Institution

Barcelona Design Inc., Newark, CA, USA

fYear

2003

fDate

21-24 Sept. 2003

Firstpage

377

Lastpage

380

Abstract

We describe the global optimization of phase-locked loop (PLL) circuits using geometric programming (GP). Equations for the jitter, frequency range, and power of the PLL are presented in GP form. An array of PLL circuits was automatically generated using this technique in a 0.18 μm, 1.8 V CMOS process. Silicon measurements show good agreement with the model. The results include a 1.9 GHz PLL with a period jitter of 2.2 ps RMS and an accumulated jitter of 6.2 ps RMS, consuming 10.8 mW.

Keywords

CMOS analogue integrated circuits; UHF integrated circuits; circuit optimisation; geometric programming; integrated circuit design; jitter; phase locked loops; 0.18 micron; 1.8 V; 1.9 GHz; 10.8 mW; CMOS; PLL array; PLL frequency range; PLL global optimization; accumulated jitter; automated analog circuit design; geometric programming; period jitter; phase-locked loop circuits; CMOS process; Circuits; Design optimization; Equations; Frequency; Jitter; Phase locked loops; Semiconductor device modeling; Silicon; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003

Print_ISBN

0-7803-7842-3

Type

conf

DOI

10.1109/CICC.2003.1249422

Filename

1249422