Programmable and automatically adjustable on-die terminator for DDR3-SRAM interface

A new programmable and automatically adjustable off-chip driver (OCD) and on-die terminator (ODT) for DDR3-SRAM interface are proposed, to widen the valid data widow. The proposed OCD fills the role of the ODT, and the OCD and the ODT play a role in the ESD protection circuit. This application of 72 Mb DDR3-SRAM provides a 1.5 GHz data rate, and the valid data window of the DDR input signal is 540 ps. The proposed programmable impedance controller (PIC) maintains constant resistance of the ODT within a 3% variation, and supports DDR3-SRAM mode. A new scheme of updating impedance control codes to maintain uniform impedance and a stable power-up sequence for the ODT are also suggested.