Title :
A 12-bit 20-MS/s pipelined ADC with nested digital background calibration
Author :
Wang, X. ; Hurst, P.J. ; Lewis, S.H.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
Abstract :
A 12-b 20-MS/s pipelined ADC is calibrated using an algorithmic ADC, which is itself calibrated. With background calibration, the peak SNDR and SFDR of the pipeline are 70.8 dB and 93.3 dB, respectively. The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm2 in 0.35 μm CMOS.
Keywords :
CMOS integrated circuits; analogue-digital conversion; calibration; pipeline processing; 0.35 micron; 254 mW; 3.3 V; ADC nested digital background calibration; CMOS; SFDR; algorithmic ADC; peak SNDR; pipelined ADC; Application specific integrated circuits; Calibration; Data mining; Force measurement; Negative feedback; Pipelines; Prototypes; Quantization; Redundancy;
Conference_Titel :
Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003
Print_ISBN :
0-7803-7842-3
DOI :
10.1109/CICC.2003.1249429
