Title :
A 9b 165MS/s 1.8V pipelined ADC with all digital transistors amplifier
Author :
Amourah, Mezyad ; Bilhan, Haydar ; Ying, Feng ; Fang, Lieyi ; Xu, Gonggui ; Chandrasekaran, Ramesh ; Geiger, Randall
Author_Institution :
Barcelona Design Inc, Newark, CA, USA
Abstract :
A 9 bit, 1.8 V, 165 MS/s pipelined ADC was built in a 0.21 μm CMOS digital process. The inter-stage amplifier in this converter was built using all digital transistors. To get sufficient gain with digital transistors, a self-adjusting positive feedback operational amplifier, that shows low sensitivity to output swing, was used. The ADC consumed a total power of 90 mW when operated at full speed.
Keywords :
CMOS integrated circuits; analogue-digital conversion; circuit feedback; operational amplifiers; pipeline processing; 0.21 micron; 1.8 V; 90 mW; CMOS digital process; all digital transistor amplifier; digital transistor gain; inter-stage amplifier; low output swing sensitivity; operational amplifier; pipelined ADC; self-adjusting positive feedback; Capacitors; Circuits; Costs; Low voltage; Operational amplifiers; Output feedback; Power dissipation; Signal sampling; Switches; Threshold voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003
Print_ISBN :
0-7803-7842-3
DOI :
10.1109/CICC.2003.1249432
