Title :
A 2.2 Gbps CMOS look-ahead DFE receiver for multidrop channel with pin-to-pin time skew compensation
Author :
Soh, Young-Soo ; Bae, Seung-Jun ; Park, Hong-June ; Kim, Chang-Hyun ; Cho, SOO-In
Author_Institution :
Dept. EE, Pohang Univ. of Sci. & Technol., South Korea
Abstract :
A CMOS LADFE (look-ahead decision feedback equalization) receiver with a pin-to-pin time skew compensation was proposed and implemented for high-speed chip-to-chip communication such as multi-drop DRAM interface. The look-ahead scheme in DFE input buffer increased the maximum data rate from 1.4 Gbps to 2.2 Gbps. Different sampling clock was synthesized for each pin by using an ×2 over-sampling scheme. Active chip area per pin is 100 μm×800 μm with a 2.5 V, 0.25 μm CMOS process.
Keywords :
CMOS integrated circuits; DRAM chips; clocks; decision feedback equalisers; integrated circuit interconnections; integrated circuit testing; radio receivers; signal sampling; 0.25 micron; 1.4 Gbit/s; 100 micron; 2.2 Gbit/s; 2.5 V; 800 micron; CMOS LADFE receiver; CMOS look-ahead DFE receiver; DFE input buffer; active chip area per pin; high-speed chip-to-chip communication; look-ahead decision feedback equalization; maximum data rate; multi-drop DRAM interface; multidrop channel; over-sampling scheme; pin-to-pin time skew compensation; sampling clock synthesis; Bandwidth; CMOS technology; Clocks; Decision feedback equalizers; Delay; Feedback loop; Phase detection; Sampling methods; Timing; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003
Print_ISBN :
0-7803-7842-3
DOI :
10.1109/CICC.2003.1249443
