Compact FPGA-based systolic array architecture suitable for vision systems

Motion estimation constitutes a significant computational part of video compression standards such as MPEG4. The present work focuses on the development of a reconfigurable systolic-based architecture implementing the full search block matching algorithm which is highly computing intensive and requires a large bandwidth to obtain real-time performance. The architecture comprises a smart memory scheme to reduce the number of access to data memory and router elements to handle data movement among different structures inside the same architecture, adding the possibility of chaining interconnection of multiple processing blocks. Every PE in the array includes a double ALU in order to search multiple macro-blocks in parallel. The functionality has been extended to support operations involved in some other low-level image algorithms. Results show that a peak performance in the order of 9 GOPS can be achieved