Use of SPIDER for the identification and analysis of process induced damage in 0.35 μm transistors

Author

Aum, Paul ; Li, Xiaoyu ; Prabhakar, V. ; Brozek, Toinasz ; Viswanathan, C.R.

Author_Institution

SEMATECH, Austin, TX, USA

fYear

1995

fDate

22-25 Mar 1995

Firstpage

1

Lastpage

4

Abstract

The paper presents a case study of the use of the SEMATECH SPIDER test structure to evaluate and identify critical damage producing plasma process steps in the fabrication of n- and p-MOS devices manufactured with a 0.35 μm CMOS line with 6.5 nm oxide. Electrical characterization of transistor modules enabled the identification of contact etch step as the principal damage producing step for the technology under investigation. The results on HC reliability degradation in CMOS devices are in agreement with the direct observations of oxide degradation, showing that the nature of the damage is of the charging type

Keywords

CMOS integrated circuits; integrated circuit technology; integrated circuit testing; sputter etching; 0.35 micron; CMOS devices; SEMATECH SPIDER test; contact etch; damage; electrical characterization; fabrication; hot carrier reliability degradation; n-MOS devices; oxide degradation; p-MOS devices; plasma processing; transistor modules; CMOS process; Contacts; Degradation; Fabrication; Manufacturing processes; Plasma applications; Plasma devices; Plasma materials processing; Pulp manufacturing; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1995. ICMTS 1995. Proceedings of the 1995 International Conference on

Conference_Location

Nara

Print_ISBN

0-7803-2065-4

Type

conf

DOI

10.1109/ICMTS.1995.513935

Filename

513935