A reversible instruction set architecture and algorithms

We describe a reversible instruction set architecture using recently developed reversible logic design techniques. Such an architecture has the dual advantage of being able to run backwards and of being, in theory, implementable so as to dissipate less than log 2 kT joules per bit operation. We analyze several basic control structures and algorithms on the architecture, showing that, for example, a sorting algorithm need only dissipate O(n log n) bits even though it makes O(n ²) comparisons