Optimization of Static Power, Leakage Power and Delay of Full Adder Circuit Using Dual Threshold MOSFET Based Design and T-Spice Simulation

Optimization of power and delay is very important issue in low-voltage and low-power applications. In this paper, we use the dual-threshold technique to reduce leakage power by assigning a high-threshold voltage to some transistors and low-threshold to some others. Here, the polarity of the MOSFETs is considered as the selection criteria for assigning threshold. In order to achieve the best leakage power, average power and delay performance, different combinations of threshold are tried in N-net and P-net. The circuit considered for simulations is 28T full adder circuit. The paper also include simulated results for different combinations using TSPICE simulator.