New FPGA architecture for bit-serial pipeline datapath

In this paper, we present our work on the design of a new FPGA architecture targeted for high-performance bit-serial pipeline datapath. Bit-parallel systems introduce large routing area overhead which is especially critical in using FPGAs, where the device utilization, and operation frequency become low because of large routing penalty. Here we propose a new FPGA architecture for high-performance bit-serial pipeline datapaths, which are very efficient in routing. Also, we refine our LUT architecture in order to efficiently implement shift registers which are required in large numbers in some bit-serial designs. Modified lookup table have two modes, combinatorial logic and shift register. Bit-serial datapath can be implemented on less number of CLBs