The impact of device type and sizing on phase noise mechanisms [MOS VCOs]

Phase noise mechanisms in integrated LC voltage-controlled oscillators (VCOs) using MOS transistors are investigated. The degradation in phase noise due to bias noise is shown to be a function of MOS device sizing. By exploiting this dependence, bias noise contributions to phase noise are minimized by design rather than through filtering. Concentrating on the remaining fundamental noise sources in the MOS cross-coupled pair, experimental results and reasoning are presented that explain why 0.18 μm PMOS devices show better phase noise than 0.18 μm NMOS devices in both the 1/f³ and 1/f² regions. A 5.3 GHz all-PMOS VCO topology demonstrates measured phase noise of -122 dBc/Hz at 1 MHz offset while dissipating 13.5 mW from a 1.8 V supply.