Defect parameter extraction in backend process steps using a multilayer checkerboard test structure

Author

Hess, Christopher ; Weiland, Larg H.

Author_Institution

Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany

fYear

1995

fDate

22-25 Mar 1995

Firstpage

51

Lastpage

56

Abstract

To control defect appearance in numerous conducting layers of backend process steps, a novel multilayer checkerboard test structure (MCTS) is presented. The separation and localization of defects-causing electrically detectable intralayer short circuits as well as interlayer short circuits-is achieved by dividing the chip area into distinguishable small subchips inside given standard boundary pads without using any active semiconductor devices. The precise localization facilitates a versatile optical defect parameter extraction

Keywords

integrated circuit interconnections; integrated circuit metallisation; integrated circuit testing; backend process steps; conducting layers; defect parameter extraction; interlayer short circuits; intralayer short circuits; multilayer checkerboard test structure; optical parameter extraction; Circuit testing; Fault tolerance; Integrated optics; Nonhomogeneous media; Optical devices; Optical sensors; Parameter extraction; Photonic integrated circuits; Process control; Semiconductor devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1995. ICMTS 1995. Proceedings of the 1995 International Conference on

Conference_Location

Nara

Print_ISBN

0-7803-2065-4

Type

conf

DOI

10.1109/ICMTS.1995.513944

Filename

513944