Title :
A low-power 0.13μm CMOS OC-48 SONET and XAUI compliant SERDES
Author :
Wadhwa, R. ; Aggarwal, A. ; Edwards, J. ; Ehlert, M. ; Hoehn, J. ; Miao, G. ; Lakshmikumar, K. ; Khoury, Joud
Author_Institution :
Multilink Technol. Corp., Somerset, NJ, USA
Abstract :
The design of a continuous rate octal 1.0 to 3.2 Gb/s serializer/deserializer circuit that meets SONET and XAUI requirements is presented. The performance of the SERDES surpasses stringent OC-48 jitter generation and tolerance specifications. This is achieved with the use of a master-slave PLL tuning scheme and meticulous attention to layout and isolation techniques. Implemented in a 0.13 μm digital CMOS technology, the part exhibits less than 5 mUI r.m.s. jitter and the 1.2 mm2 transceiver dissipates 160 mW.
Keywords :
CMOS digital integrated circuits; SONET; digital phase locked loops; jitter; low-power electronics; 0.13 micron; 1.0 to 3.2 Gbit/s; 160 mW; CMOS serializer/deserializer circuit; OC-48 SONET; XAUI; continuous rate octal SERDES; jitter; low-power SERDES; master-slave PLL tuning scheme; transceiver; CMOS technology; Clocks; Jitter; Master-slave; Phase locked loops; SONET; Transceivers; Transmitters; Tuning; Voltage-controlled oscillators;
Conference_Titel :
Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003
Print_ISBN :
0-7803-7842-3
DOI :
10.1109/CICC.2003.1249464
