A 62.5 Gb/s multi-standard SerDes IC

Author

Partovi, Hamid ; Evans, Bill ; Wilson, Tom ; Shelton, Scott ; Naviasky, Eric ; Sanjeevi, Ethiraj ; Wen, Yongli ; Gopalakrishnan, Karthik ; Chokkalingam, Sivaraman ; Thompson, Hugh ; Casas, Mike ; Ye, Lingting ; Hufford, Mike ; Qiu, Yujing ; Williams, Mich

Author_Institution

Mixed Signal IC Dev., Infineon Technol., San Jose, CA, USA

fYear

2003

fDate

21-24 Sept. 2003

Firstpage

585

Lastpage

588

Abstract

This paper describes a 20-lane 62.5 Gb/s SerDes designed as an interface between the 40G, or quad 10G Optics, and a downstream framer device. Transmit and receive clocks are derived from an LC-based PLL with a wideband RMS jitter below 2.5 ps. Timing recovery uses a 2^nd order loop and includes over-sampled ΔΣ techniques to achieve both narrowband filtering and excellent jitter tolerance. To support backplane applications, line driver and receiver incorporate preemphasis and equalization respectively.

Keywords

CMOS integrated circuits; band-pass filters; demultiplexing equipment; integrated circuit measurement; jitter; multiplexing equipment; network interfaces; phase locked loops; sigma-delta modulation; signal sampling; synchronisation; system buses; 62.5 Gbit/s; CMOS technology; LC-based PLL; SerDes interface; Timing recovery; Transmit clocks; backplane applications; clocks; downstream framer device; equalization; jitter tolerance; line driver; multi-standard SerDes IC; narrow-band filtering; over-sampled AE techniques; pre-emphasis; receiver; wideband RMS jitter; Clocks; Narrowband; Optical design; Optical devices; Optical filters; Optical receivers; Phase locked loops; Photonic integrated circuits; Timing jitter; Wideband;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003

Print_ISBN

0-7803-7842-3

Type

conf

DOI

10.1109/CICC.2003.1249466

Filename

1249466