An in-process monitoring method for electromigration resistance of multilayered metal interconnects

Author

Fujii, Takako ; Itoh, Tosiki ; Ishizuka, Hiroyasu ; Okuyama, Kousuke ; Kubota, Katsuhiko

Author_Institution

Semicond. & Integrated Circuit Div., Hitachi Ltd., Tokyo, Japan

fYear

1995

fDate

22-25 Mar 1995

Firstpage

87

Lastpage

92

Abstract

This paper describes it method for monitoring electromigration (EM) resistance of multilayered metal interconnects which have been widely used in recent LSI technologies. We studied the combination of SWEAT (Standard Wafer-Level Electromigration Acceleration Test) patterns and the BEM (Breakdown Energy of Metal) method. We found that SWEAT pattern has a threshold length in its narrow portion to grow voids induced by EM, and optimized the conditions for the BEM method in terms of temperature and ramping rate. We have realized an in-process EM monitoring method which takes 4 minutes per sample at room temperature using the above combination

Keywords

electromigration; integrated circuit interconnections; integrated circuit testing; large scale integration; life testing; monitoring; BEM method; Breakdown Energy of Metal; LSI technologies; SWEAT pattern; Standard Wafer-Level Electromigration Acceleration Test; electromigration resistance; in-process monitoring; multilayered metal interconnects; voids; Artificial intelligence; Electric breakdown; Electromigration; Integrated circuit interconnections; Microcomputers; Monitoring; Optimization methods; Stress; Temperature; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1995. ICMTS 1995. Proceedings of the 1995 International Conference on

Conference_Location

Nara

Print_ISBN

0-7803-2065-4

Type

conf

DOI

10.1109/ICMTS.1995.513951

Filename

513951