Title :
A run-time reconfigurable engine for image interpolation
Author :
Hudson, Rhett D. ; Lehn, David I. ; Athanas, Peter M.
Author_Institution :
Bradley Dept. of Electr. & Comput. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
Abstract :
Custom Computing Machines (CCM´s) have demonstrated significant performance advantages over general-purpose processors for certain classes of problems. However, problems can always be found which require computational resources in excess of those available on a particular CCM. Exploiting the reconfigurable nature of FPGAs can alleviate this limitation. The FPGAs´ computational resources can be time multiplexed to allow different portions of the computation to execute in stages. Intermediate results are saved to memory and passed on to later stages of the computation. This technique is used in this work to implement an image interpolation engine on the Xilinx XC6264 Reference Board. The engine utilizes 2-5-2 splines to take advantage of their computationally convenient powers-of-two arithmetic
Keywords :
field programmable gate arrays; image processing; interpolation; reconfigurable architectures; splines (mathematics); 2-5-2 splines; FPGAs; Xilinx XC6264 Reference Board; image interpolation; reconfigurable engine; Application specific integrated circuits; Arithmetic; Engines; Field programmable gate arrays; Hardware; Interpolation; Libraries; Prototypes; Random access memory; Runtime;
Conference_Titel :
FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on
Conference_Location :
Napa Valley, CA
Print_ISBN :
0-8186-8900-5
DOI :
10.1109/FPGA.1998.707886
