Title :
Modeling and analysis of high-speed links
Author :
Stojanovic, Vladimir ; Horowitz, Mark
Author_Institution :
Stanford Univ., CA, USA
Abstract :
Very low bit error rate (BER) requirements for the operation of a high-speed link system require a very precise analysis of the link performance in order to prevent unrealistic specifications on both IC design and communication algorithm development. This paper presents the analysis of the noise and distortion sources in a high-speed link system, and their impact on the choice and effectiveness of different communication techniques. Phase-locked loop and clock-and-data recovery loop modeling is also described. It is shown that the most dominant noise and distortion sources are colored and bounded, as opposed to standard unbounded Gaussian white noise assumptions, which yield large errors in the estimation of the link performance and comparison of different signaling techniques. With very low BER requirements, shape of probability distribution of noise and distortion sources and their correlations, are much more important than just their total power, which contrasts the standard analysis in communication systems.
Keywords :
distortion; error statistics; integrated circuit design; integrated circuit noise; interference (signal); multiprocessor interconnection networks; phase locked loops; probability; synchronisation; system buses; BER requirements; IC design specifications; bit error rate requirements; clock-and-data recovery loop modeling; colored bounded distortion sources; colored bounded noise sources; communication algorithm development; communication techniques; correlations; distortion sources; high-speed links; link performance analysis; modeling; noise sources; phase-locked loop modeling; probability distribution shape; signaling techniques; standard unbounded Gaussian white noise assumptions; Algorithm design and analysis; Bit error rate; Clocks; Colored noise; Gaussian noise; High speed integrated circuits; Integrated circuit noise; Noise shaping; Performance analysis; Phase locked loops;
Conference_Titel :
Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003
Print_ISBN :
0-7803-7842-3
DOI :
10.1109/CICC.2003.1249467