A fully-integrated 10.5 to 13.5 Gbps transceiver in 0.13 μm CMOS

Author

Miao, G. ; Ju, P. ; Ng, D. ; Khoury, J. ; Lakshmikumar, K.

Author_Institution

Multilink Technol. Corp., Somerset, NJ, USA

fYear

2003

fDate

21-24 Sept. 2003

Firstpage

595

Lastpage

598

Abstract

The design of a fully-integrated 10.5 to 13.5 Gbps transceiver is presented. The chip uses a half-rate architecture for both the transmitter and receiver. Duo-binary and electrical RZ pre-coding are implemented in the transmitter. The receiver uses a high-gain input buffer with a new digital offset cancellation technique to achieve 15 mVpp differential input sensitivity. Programmable phase tuning capability in the clock and data recovery (CDR) loop provides optimum data sampling instants. The transceiver occupies 8 mm² and dissipates 1 W in a 0.13 μm digital CMOS process.

Keywords

CMOS digital integrated circuits; buffer circuits; encoding; integrated circuit design; integrated circuit measurement; signal sampling; synchronisation; transceivers; 0.13 micron; 1 W; 10.5 to 13.5 Gbit/s; 15 mV; CDR loop; chip half-rate architecture; clock and data recovery loop; differential input sensitivity; digital CMOS process; digital offset cancellation technique; duo-binary pre-coding; electrical RZ pre-coding; fully-integrated transceiver; optimum data sampling instants; programmable phase tuning capability; receiver; receiver high-gain input buffer; transmitter; Bandwidth; CMOS technology; Circuit optimization; Clocks; Filters; Low voltage; Transceivers; Transmitters; Tuning; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003

Print_ISBN

0-7803-7842-3

Type

conf

DOI

10.1109/CICC.2003.1249468

Filename

1249468