In-system failure investigation on 0.18 μm high speed serial link ASIC using logic built-in self test

Author

Mechler, Jeanne Trinko ; Bulaga, Raymond ; Garlett, Jon

Author_Institution

IBM Microeletronics, Essex Junction, VT, USA

fYear

2003

fDate

21-24 Sept. 2003

Firstpage

613

Lastpage

616

Abstract

In this exciting chip debug investigation, a mysterious voltage sensitivity was exhibited in four out of six High Speed SerDes (HSS) serial link IP blocks on a 0.18 μm prototype ASIC chip. A number of noise and circuit failure theories were hypothesized. The investigators conducted experiments in both the device manufacturing test and system verification card environment. Ultimately, the use of the at-speed logic built-in self test (LBIST) present in the HSS IP blocks exercised in the system environment allowed the team to crack the case.

Keywords

application specific integrated circuits; built-in self test; failure analysis; integrated circuit reliability; integrated circuit testing; logic testing; production testing; sensitivity analysis; 0.18 micron; HSS IP blocks; High Speed SerDes serial link IP blocks; LBIST; at-speed logic built-in self test; chip debug; circuit failure; device manufacturing test; high speed serial link ASIC; in-system failure investigation; logic built-in self test; noise; prototype ASIC chip; system verification card environment; voltage sensitivity; Application specific integrated circuits; Automatic testing; Circuit noise; Circuit testing; Logic testing; Manufacturing; Prototypes; System testing; Voltage; Working environment noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003

Print_ISBN

0-7803-7842-3

Type

conf

DOI

10.1109/CICC.2003.1249471

Filename

1249471