Title :
Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process
Author :
Hazucha, Peter ; Karnik, T. ; Walstra, Steven ; Bloechel, Bradley ; Tschanz, James ; Maiz, Jose ; Soumyanath, Krishnamurthy ; Dermer, G. ; Narendra, Siva ; De, Vivek ; Borkar, Shekhar
Author_Institution :
Intel Labs., Intel Corp., Hillsboro, OR, USA
Abstract :
We measured neutron soft error rate (SER) of hardened and standard latches in a 90 nm dual-Vt CMOS process. The hardened latch demonstrated over 10× lower SER at no speed degradation. Energy penalty can be minimal for standard-latch transistor sizes at least twice the minimum size. We analyzed the effects of recovery time and leakage on the SER robustness.
Keywords :
CMOS integrated circuits; flip-flops; integrated circuit testing; leakage currents; logic testing; neutron effects; radiation hardening (electronics); 90 nm; SER robustness; SER tolerant; dual-Vt CMOS process; energy penalty; hardened latches; leakage effects; neutron soft error rate; recovery time effects; speed degradation; standard latches; CMOS process; Circuits; Clocks; Cosmic rays; Degradation; Flip-flops; Latches; Neutrons; Robustness; Space technology;
Conference_Titel :
Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003
Print_ISBN :
0-7803-7842-3
DOI :
10.1109/CICC.2003.1249472
