Automating production of run-time reconfigurable designs

Author

Shirazi, Nabeel ; Luk, Wayne ; Cheung, Peter Y K

Author_Institution

Dept. of Comput., Imperial Coll. of Sci., Technol. & Med., London, UK

fYear

1998

fDate

15-17 Apr 1998

Firstpage

147

Lastpage

156

Abstract

This paper describes a method that automates a key step in producing run-time reconfigurable designs: the identification and mapping of reconfigurable regions. In this method, two successive circuit configurations are matched to locate the components common to them, so that reconfiguration time can be minimized. The circuit configurations are represented as a weighted bipartite graph, to which an efficient matching algorithm is applied. Our method, which supports hierarchical and library-based design, is device-independent and has been tested using Xilinx 6200 FPGAs. A number of examples in arithmetic, pattern matching and image processing are selected to illustrate our approach

Keywords

field programmable gate arrays; image processing; pattern matching; reconfigurable architectures; Xilinx 6200 FPGAs; circuit configurations; image processing; library-based design; mapping; matching algorithm; pattern matching; run-time reconfigurable designs; weighted bipartite graph; Arithmetic; Bipartite graph; Circuit testing; Design engineering; Educational institutions; Field programmable gate arrays; Image processing; Pattern matching; Production; Runtime;

fLanguage

English

Publisher

ieee

Conference_Titel

FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on

Conference_Location

Napa Valley, CA

Print_ISBN

0-8186-8900-5

Type

conf

DOI

10.1109/FPGA.1998.707892

Filename

707892