Title :
Standby voltage scaling for reduced power
Author :
Calhoun, B. ; Chandrakasan, A.
Author_Institution :
Dept. of Electr. Eng., MIT, Cambridge, MA, USA
Abstract :
Lowering VDD during standby mode reduces power by decreasing both voltage and current. Measurements of a 0.13 μm test chip show that reducing VDD to near the point where state is lost gives the best power savings. We propose closed-loop voltage scaling that uses "canary" flip-flops for achieving these savings. This approach provides over 2× higher savings than optimal open-loop approaches without loss of state.
Keywords :
flip-flops; integrated circuit design; leakage currents; low-power electronics; 0.13 micron; canary flip-flops; closed-loop voltage scaling; optimal open-loop approaches; power consumption; power savings; reduced current; reduced voltage; standby mode; standby voltage scaling; state loss; test chip; Combinational circuits; Diodes; Emergency power supplies; Equations; Flip-flops; Gate leakage; Logic testing; Sequential circuits; Subthreshold current; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003
Print_ISBN :
0-7803-7842-3
DOI :
10.1109/CICC.2003.1249477
