TPCSPC decoding over coded partial-response channels

In this paper, we consider turbo product codes with single-parity-check component codes as an low-complexity coding scheme for magnetic recording systems. Based on the observation that TPCSPC can be viewed as a special type of regular LDPC codes, three message-passing schedules of the sum-product algorithm (SPA) are studied. It is shown that the standard row-column decoding algorithm in the literature is essentially the same as the serial check-updating schedule. By viewing the code graph from a different perspective, we propose a serial bit-updating schedule that uses the MacLaurin Series expansion to approximate the computationally intensive check operation. The proposed algorithm converges faster than the parallel decoding schedule and can be implemented efficiently in hardware by using high-speed adders, comparators, and shift registers.