Architecture and Software Implementation of HDTV Video Decoder on a Singlechip, MPEG Decoder

Author

Ye, Yuhuang ; Li, Yuanjiu ; Su, Kaixiong

Author_Institution

Dept. of Inf. & Commu. Eng., Fuzhou Univ.

fYear

2006

fDate

26-28 July 2006

Firstpage

226

Lastpage

230

Abstract

This paper presents the architecture and software design of HDTV video decoder on a 200-MHz single-chip microprocessor. First, the paper analyzes the hardware architecture of video decoder system on this MPEG decoder and describes the function of each module in this system, including the PES parser, decode pipeline, SC analyzer, and display processor. Then it gives the software control and implementation of this video decoder. This video decoder meets the requirements for MPEG-2 MP@HL real-time decoding. The outcome of this paper should be helpful to the design of HDTV set top box

Keywords

high definition television; microprocessor chips; software architecture; video codecs; video coding; HDTV set top box; HDTV video decoder; MPEG decoder; PES parser; SC analyzer; display processor; hardware architecture; single-chip microprocessor; software architecture; software design; Computer architecture; Decoding; Digital TV; Displays; HDTV; Hardware; High definition video; Pipelines; Streaming media; Videoconference; HDTV; MPEG-2; set top box; video decoder;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Graphics, Imaging and Visualisation, 2006 International Conference on

Conference_Location

Sydney, Qld.

Print_ISBN

0-7695-2606-3

Type

conf

DOI

10.1109/CGIV.2006.23

Filename

1663796