Title :
Vertical, fully-depleted, surrounding gate MOSFETs on sub-0.1 /spl mu/m thick silicon pillars
Author :
Auth, C.P. ; Plummer, J.D.
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
Abstract :
Fabrication of MOSFETs on the sidewall of ultra-thin silicon pillars has been shown. The structures employ a self-aligned drain to enable the use of minimum definable pillar widths. Additionally by moving to a vertical structure, the high current density of surrounding gate MOSFETs can be achieved on conventional bulk substrates, and self-aligned gates can be maintained. These devices exhibit near ideal subthreshold slopes and low DIBL values, making them ideal for low power applications.
Keywords :
MOSFET; semiconductor technology; silicon-on-insulator; 0.1 micron; DIBL; SOI structure; Si; current density; fabrication; fully-depleted vertical surrounding gate MOSFET; low power applications; self-aligned technology; subthreshold slope; ultra-thin silicon pillar; Costs; Etching; Implants; Leakage current; MOSFETs; Power supplies; Semiconductor devices; Silicon; Substrates; Threshold voltage;
Conference_Titel :
Device Research Conference, 1996. Digest. 54th Annual
Conference_Location :
Santa Barbara, CA, USA
Print_ISBN :
0-7803-3358-6
DOI :
10.1109/DRC.1996.546333
