Vertical, fully-depleted, surrounding gate MOSFETs on sub-0.1 /spl mu/m thick silicon pillars

Fabrication of MOSFETs on the sidewall of ultra-thin silicon pillars has been shown. The structures employ a self-aligned drain to enable the use of minimum definable pillar widths. Additionally by moving to a vertical structure, the high current density of surrounding gate MOSFETs can be achieved on conventional bulk substrates, and self-aligned gates can be maintained. These devices exhibit near ideal subthreshold slopes and low DIBL values, making them ideal for low power applications.