Title :
Efficient extraction of metal parasitic capacitances
Author :
Gaston, G.J. ; Daniels, I.G.
Author_Institution :
GEC Plessey Semicond. Ltd., Plymouth, UK
Abstract :
Accurate extraction of parasitic capacitances associated with fine pitch metallisation layers is essential in the design of ULSI ICs. This paper reports on investigation of the impact of test structure design on extracted values for inter-layer and intra-layer capacitances; the influence of topography is also reviewed. Recommendations are made for optimum test structure design and it is indicated how such structures can provide an efficient means of assessing dielectric planarisation. This provides process engineers with a important, nondestructive means of assessing and monitoring a key technology parameter. The use of three-dimensional simulation in backend process optimisation is briefly described
Keywords :
ULSI; capacitance measurement; fine-pitch technology; integrated circuit metallisation; integrated circuit testing; ULSI ICs; backend process optimisation; dielectric planarisation; fine pitch metallisation layers; inter-layer capacitance; intra-layer capacitance; metal parasitic capacitances; nondestructive monitoring; test structure; three-dimensional simulation; topography; Capacitance measurement; Circuits; Dielectric measurements; Metallization; Parasitic capacitance; Planarization; Substrates; Surfaces; Testing; Ultra large scale integration;
Conference_Titel :
Microelectronic Test Structures, 1995. ICMTS 1995. Proceedings of the 1995 International Conference on
Conference_Location :
Nara
Print_ISBN :
0-7803-2065-4
DOI :
10.1109/ICMTS.1995.513964
