DocumentCode
2346922
Title
Implementation of simultaneous video decoding on multicore processor
Author
Kawamura, Yuki ; Manabe, Yasutake ; Onoye, Takao ; Ohara, Kazuto ; Okada, Hiroyuki ; Keshi, Ikuo
Author_Institution
Grad. Sch. of Inf. Sci. & Technol., Osaka Univ., Suita, Japan
fYear
2010
fDate
3-5 March 2010
Firstpage
1
Lastpage
4
Abstract
An implementation of simultaneous video decoding is described, which is based on a heterogeneous multicore processor. Appropriate task division and assignment to processor cores are explored for efficient execution on the multicore processor. In addition, a set of mechanisms to reduce video decoding complexity is employed, i.e. simplified IDCT, VLD skip, and B-frame skip. Experimental results demonstrate that simultaneous decoding of 40 MPEG-2 HD streams or 172 MPEG-2 SD streams can be achieved by the proposed approach.
Keywords
microprocessor chips; multiprocessing systems; video coding; B-frame skip mechanism; IDCT mechanism; MPEG-2 HD streams; MPEG-2 SD streams; VLD skip mechanism; multicore processor; simultaneous video decoding; Decoding; Multicore processing;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications, Control and Signal Processing (ISCCSP), 2010 4th International Symposium on
Conference_Location
Limassol
Print_ISBN
978-1-4244-6285-8
Type
conf
DOI
10.1109/ISCCSP.2010.5463332
Filename
5463332
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