Implementation of simultaneous video decoding on multicore processor

An implementation of simultaneous video decoding is described, which is based on a heterogeneous multicore processor. Appropriate task division and assignment to processor cores are explored for efficient execution on the multicore processor. In addition, a set of mechanisms to reduce video decoding complexity is employed, i.e. simplified IDCT, VLD skip, and B-frame skip. Experimental results demonstrate that simultaneous decoding of 40 MPEG-2 HD streams or 172 MPEG-2 SD streams can be achieved by the proposed approach.