Title :
A reconfigurable multiplier array for video image processing tasks, suitable for embedding in an FPGA structure
Author :
Haynes, Simon D. ; Cheung, Peter Y K
Author_Institution :
Dept. of Electr. & Electron. Eng., Imperial Coll. of Sci., Technol. & Med., London, UK
Abstract :
This paper presents a design for a reconfigurable multiplier array. The multiplier is constructed using an array of 4 bit Flexible Array Blocks (FABs), which could be embedded within a conventional FPGA structure. The array can be configured to perform a number of 4n×4m bit signed/unsigned binary multiplications. We have estimated that the FABs are about 25 times more efficient in area than the equivalent multiplier implemented using a conventional FPGA structure alone
Keywords :
digital arithmetic; digital signal processing chips; field programmable gate arrays; image processing; multiplying circuits; reconfigurable architectures; FPGA; Flexible Array Blocks; binary multiplications; reconfigurable multiplier array; Acceleration; Application software; Arithmetic; Biomedical imaging; Costs; Educational institutions; Field programmable gate arrays; Hardware; Image processing;
Conference_Titel :
FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on
Conference_Location :
Napa Valley, CA
Print_ISBN :
0-8186-8900-5
DOI :
10.1109/FPGA.1998.707900
