DocumentCode
2346986
Title
A highly linear CMOS buffer circuit with an adjustable output impedance
Author
Koutani, Masato ; Fujimoto, Yoshihisa ; Miyamoto, Masayuki
Author_Institution
Corporate Res. & Dev. Group, Sharp Corp., Nara, Japan
fYear
2003
fDate
21-24 Sept. 2003
Firstpage
685
Lastpage
688
Abstract
An output buffer circuit with an adjustable output impedance and high linearity is presented. The buffer circuit employs two kinds of feedback strategies, which enable it to drive a low impedance load without power increase. A differential buffer circuit with 20-ohm output impedance has been fabricated in a 0.25-μm CMOS process. The measured IIP3 is over 30 dBm for frequencies up to 100 MHz and the power consumption is 93.1 mW with a 3.3-V power supply.
Keywords
CMOS analogue integrated circuits; buffer circuits; circuit feedback; impedance matching; linearisation techniques; radiofrequency integrated circuits; 0.25 micron; 100 MHz; 20 ohm; 3.3 V; 93.1 mW; IIP3; adjustable output impedance; differential buffer; feedback; highly linear CMOS buffer; impedance matching; low impedance load; output buffer circuit; CMOS process; Feedback circuits; Filters; Frequency conversion; Impedance; Linearity; Mixers; TV; Transconductance; Tuners;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003
Print_ISBN
0-7803-7842-3
Type
conf
DOI
10.1109/CICC.2003.1249486
Filename
1249486
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