Title :
Modeling of jitter in bang-bang clock and data recovery circuits
Author :
Lee, Jri ; Kundert, Kenneth S. ; Razavi, Behzad
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Abstract :
This paper presents an approach to analyzing bang-bang CDR loops, predicting performance aspects such as jitter transfer, jitter tolerance, jitter generation, and the bit error rate. A 1-Gb/s CDR circuit realized in 0.35-μm CMOS technology validates the theoretical results.
Keywords :
CMOS digital integrated circuits; circuit simulation; error statistics; integrated circuit modelling; jitter; phase detectors; synchronisation; 0.35 micron; 1 Gbit/s; CMOS; bang-bang CDR loops; bang-bang clock /data recovery circuits; binary phase detectors; bit error rate; jitter generation; jitter modeling; jitter tolerance; jitter transfer; Bit error rate; CMOS technology; Circuits; Clocks; Jitter; Latches; Metastasis; Oscillators; Performance analysis; Semiconductor device modeling;
Conference_Titel :
Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003
Print_ISBN :
0-7803-7842-3
DOI :
10.1109/CICC.2003.1249492
