On-package decoupling optimization with package macromodels

Author

Zheng, Hui ; Krauter, Byron ; Pileggi, Lawrence

Author_Institution

Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

fYear

2003

fDate

21-24 Sept. 2003

Firstpage

723

Lastpage

726

Abstract

Suppressing clock-gating-induced noise at the chip-package interface is one of the most challenging power distribution integrity issues. In this paper, accurate and efficient assessment of the effectiveness of on-package decoupling is facilitated by package macromodels which compactly represent packaging parasitics among multiple on-package decoupling and on-chip ports. Based on such assessment, a simulated-annealing-based optimization procedure is developed with the goal of finding the most cost-effective on-package decoupling while meeting the noise budget.

Keywords

capacitors; circuit optimisation; integrated circuit design; integrated circuit modelling; integrated circuit noise; integrated circuit packaging; simulated annealing; chip-package interface; clock-gating-induced noise suppression; decoupling capacitors; multiple on-chip ports; on-package decoupling optimization; package macromodels; packaging parasitics; power distribution integrity; simulated-annealing; Application specific integrated circuits; Capacitors; Clocks; Conductors; Coupling circuits; Impedance; Inductance; Magnetic analysis; Semiconductor device noise; Semiconductor device packaging;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003

Print_ISBN

0-7803-7842-3

Type

conf

DOI

10.1109/CICC.2003.1249495

Filename

1249495