Title :
Understanding clustering of defects in a sub-0.5 μm CMOS fabricator
Author :
Satya, Akella V S
Author_Institution :
IBM Corp., East Fishkill, NY, USA
Abstract :
Over two decades of bipolar-experience has previously alerted one to the fact that the extent of defect clustering, assumed in the CMOS yield models, may not hold for defects monitored on microelectronic test structures (MTS). Tracing the defect clustering from inline CMOS MTS, we now describe a viable yield prediction model using data from the various inline monitors, which also helps reconcile the questions raised earlier. Such a yield-bridge between the MTS-data and the product yield establishes the validity of the yield model and assumptions therein
Keywords :
CMOS integrated circuits; integrated circuit modelling; integrated circuit testing; integrated circuit yield; 0.5 micron; CMOS yield models; defect clustering; inline monitor data; microelectronic test structures; submicron CMOS fabricator; yield prediction model; Bridge circuits; CMOS process; Erbium; Microelectronics; Monitoring; Predictive models; Random access memory; Redundancy; Semiconductor device modeling; Testing;
Conference_Titel :
Microelectronic Test Structures, 1995. ICMTS 1995. Proceedings of the 1995 International Conference on
Conference_Location :
Nara
Print_ISBN :
0-7803-2065-4
DOI :
10.1109/ICMTS.1995.513990
