A new hierarchical RSM for TCAD-based device design to predict CMOS development

Author

Sato, Hisako ; Tsuneno, Katsumi ; Aoyama, Kimiko ; Nakamura, Takahide ; Kunitomo, Hisaaki ; Masuda, Hiroo

Author_Institution

Hitachi Ltd., Tokyo, Japan

fYear

1995

fDate

22-25 Mar 1995

Firstpage

299

Lastpage

302

Abstract

A new methodology in simulation-based CMOS process designs has been proposed, using a hierarchical RSM (Response Surface Method) and efficient experimental calibrations. The new design methodology has been verified in a half-micron CMOS process/device development using the test structure, which results in reliable prediction of the threshold voltage (Vth) and drain current (Ids) within 0.01 V and 0.84% errors, respectively. This method has also reduced simulation works to about one half required by the conventional RSM. TCAD based RSM is applied for predicting quarter-micron CMOS development

Keywords

CMOS integrated circuits; electronic engineering computing; semiconductor process modelling; 0.25 micron; 0.5 micron; CMOS development prediction; TCAD-based device design; design methodology; drain current; experimental calibrations; half-micron CMOS process; hierarchical response surface method; quarter-micron CMOS; simulation-based CMOS process design; technology CAD; test structure; threshold voltage; CMOS process; Calibration; Design methodology; Intrusion detection; Microcomputers; Predictive models; Process design; Response surface methodology; Testing; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1995. ICMTS 1995. Proceedings of the 1995 International Conference on

Conference_Location

Nara

Print_ISBN

0-7803-2065-4

Type

conf

DOI

10.1109/ICMTS.1995.513991

Filename

513991