Title :
Static test compaction for IDDQ testing of sequential circuits
Author :
Higami, Yoshinobu ; Saluja, Kewal K. ; Kinoshita, Kozo
Author_Institution :
Fac. of Eng., Ehime Univ., Matsuyama, Japan
Abstract :
This paper presents a static test compaction method for IDDQ testing of sequential circuits. Target faults are bridging faults between arbitrary pair of nodes including internal nodes, signal lines, VDD and GND. In the proposed method, test subsequences are removed and replaced with shorter subsequences
Keywords :
CMOS logic circuits; automatic testing; fault diagnosis; integrated circuit testing; logic testing; sequential circuits; CMOS; GND; IDDQ testing; VDD; bridging faults; internal nodes; sequential circuits; signal lines; static test compaction; test subsequences; CMOS technology; Circuit faults; Circuit testing; Compaction; Electrical fault detection; Fault detection; Logic testing; Sequential analysis; Sequential circuits; Terminology;
Conference_Titel :
IDDQ Testing, 1998. Proceedings. 1998 IEEE International Workshop on
Conference_Location :
San Jose, CA
Print_ISBN :
0-8186-9191-3
DOI :
10.1109/IDDQ.1998.730725
