Title :
Architecture and design of a programmable 3D-integrated cellular processor array for image processing
Author :
Lopich, Alexey ; Dudek, Piotr
Author_Institution :
Sch. of Electr. & Electron. Eng., Univ. of Manchester, Manchester, UK
Abstract :
In this work we present a design of a massively-parallel cellular processor array implemented in 3D CMOS technology. The proof of concept 128×96 array device is partitioned across two custom designed layers. Additionally, three layers of DDR memory are vertically stacked and bonded underneath. The processor benefits from 358Gbit/s data rate between memory and array, as well as from high logic density, thanks to improved routing across silicon layers with Trough Silicon Vias (TSVs).
Keywords :
CMOS integrated circuits; image processing equipment; integrated circuit design; three-dimensional integrated circuits; 3D CMOS technology; TSV; bonded underneath; high logic density; image processing; programmable 3D-integrated cellular processor array; trough silicon vias; CMOS integrated circuits; CMOS technology; Educational institutions; Random access memory; Real time systems; Registers;
Conference_Titel :
VLSI and System-on-Chip (VLSI-SoC), 2011 IEEE/IFIP 19th International Conference on
Conference_Location :
Hong Kong
Print_ISBN :
978-1-4577-0171-9
Electronic_ISBN :
978-1-4577-0169-6
DOI :
10.1109/VLSISoC.2011.6081606
