Uniform carbon nanotube diameter and nanoarray pitch for VLSI of 16nm P-channel MOSFETs

Author

Sun, Yanan ; Kursun, Volkan

Author_Institution

Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China

fYear

2011

fDate

3-5 Oct. 2011

Firstpage

226

Lastpage

231

Abstract

Uniformities of carbon nanotube diameters and nanoarray pitch values of all the transistors across a chip are required to enable low cost very large scale integration (VLSI) with the carbon nanotube technology. Nanotube diameter and nanoarray pitch are concurrently optimized and unified in this paper with two different substrate bias voltages considering a wide range of p-channel transistor sizes. A performance and density metric is evaluated to identify the optimum p-type device profiles suitable for very large scale integration with a 16nm carbon nanotube transistor technology.

Keywords

MOSFET; VLSI; carbon nanotubes; VLSI; carbon nanotube transistor technology; density metric; nanoarray pitch values; p-channel MOSFET; p-channel transistor size; size 16 nm; substrate bias voltage; transistors; uniform carbon nanotube diameter; very large scale integration; Carbon nanotubes; Degradation; Electron tubes; Measurement; Substrates; Transistors; Very large scale integration; CN-MOSFET technology; Carbon nanotube very large scale integration (VLSI); substrate bias voltage; uniform nanoarray pitch; uniform nanotube diameter;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI and System-on-Chip (VLSI-SoC), 2011 IEEE/IFIP 19th International Conference on

Conference_Location

Hong Kong

Print_ISBN

978-1-4577-0171-9

Electronic_ISBN

978-1-4577-0169-6

Type

conf

DOI

10.1109/VLSISoC.2011.6081642

Filename

6081642