Topology synthesis of analog circuits with yield optimization and evaluation using pareto fronts

This paper presents a tool for automatic analog topology generation and subsequent sizing. For this purpose a multistage design flow has been developed. To synthesize new circuit topologies according to a set of given specifications, a hierarchical algorithm composes the circuits using a library of basic building blocks. A set of constraints ensures an electrically reasonable interconnection of the blocks. In the next step all generated circuits are preselected by symbolic analysis methods. The following sizing is executed with SPICE accuracy. Three main extensions are applied, compared to previous approaches. First, the symbolic analysis methodology has been improved. Second, a yield optimization has been included to the sizing step. Third, an automated evaluation of hundreds successfully sized circuits is realized through searching for the pareto optimal designs. Results are shown through two different synthesis runs, generating operational amplifier topologies.