Title :
Minimizing redundancy-based motion estimation design for high-definition
Author :
Kim, Jeong Hoon ; In Jung Lyu ; Lyu, Hyun June ; Choi, Jun Rim
Author_Institution :
Sch. of Electron. Eng., Kyungpook Nat. Univ., Daegu, South Korea
Abstract :
In this paper, the redundant data in integer motion estimation that comes from overlapping reference blocks of consecutive current macro blocks processing is eliminated to reduce memory access rate. Based on early predicted candidate in fractional motion estimation, unique interpolation processing is employed to reduce the latency by half. In addition, based on high correlation, the scheme of processing 4×8 and 4×4 block with free of cycles is proposed, so that the number of motion vectors on FME can be reduced up to 59%. Experimental results show that the proposed motion estimation design saves 16% of gate count and 65% of local memory while supporting higher encoding specification.
Keywords :
image coding; motion estimation; consecutive current macro blocks processing; fractional motion estimation; high correlation; high-definition; higher encoding specification; integer motion estimation; latency reduction; memory access rate reduction; motion vectors; overlapping reference blocks; redundancy-based motion estimation design; redundant data; unique interpolation processing; Bit rate; Computer architecture; Hardware; Logic gates; Motion estimation; PSNR; Vectors; H.264/AVC; VLSI architecture; motion estimation; video signal processing;
Conference_Titel :
VLSI and System-on-Chip (VLSI-SoC), 2011 IEEE/IFIP 19th International Conference on
Conference_Location :
Hong Kong
Print_ISBN :
978-1-4577-0171-9
Electronic_ISBN :
978-1-4577-0169-6
DOI :
10.1109/VLSISoC.2011.6081662
